RYZEN 9 3950X 色々ベンチを取ってみる

現在主流のベンチアプリの結果は探せばいくらでもあるので、Ryzen7 1700(OC)と比較した、俺得結果をまとめます。

取得環境

CPUは当然RYZEN 9 3950X。マザーボードはASUS Strix B450-I Gaming(BIOS:2901)。
CPUをOCする際はRyzen Masterを用いています。

またメモリはSanMax SMD4-U32G48M-26V-DのままですがRYZEN 7 1700では限界だった3200MHzを楽々と超えて3600動作可能に。さすがは6層基板+スロット2本のマザボとZen2メモコンに、高クロックに耐えられるSanMaxメモリ品質。

まずはCINEBENCH R20 10000超えをめざず

デフォルト状態で取ったR20の結果は9165でしたが、手動OCで試してみると10000超えできそうだったので試行錯誤した結果、CPU 4.275GHz(1.425V)/メモリOC3600MHzで何とか10067を達成。

さらなる高みを目指したいところですが、この個体はオールコア4.3GHzに高い壁があるらしくベンチを安定稼働させることができなかったため断念してます。

古いCPU-ZでRYZEN 7 1700@3.9GHzと比較

以前のページを見てみるとCPU-Z 1.78でCPUベンチを取得していたので比較してみる。以前はSingle:2227/Multi:20265、3950X(デフォルト)はSingle:2694/Multi:46222と大きくパワーアップ。
A10-6800K(OC)はSingle:1335/Multi:4600だったので10倍の処能ということになります。

RYZEN 9 3950XのCoreinfo

一体だれの需要があるかは不明ですがCoreinfoも取得しておきます。

>Coreinfo.exe
Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright (C) 2008-2014 Mark Russinovich
Sysinternals - www.sysinternals.com

AMD Ryzen 9 3950X 16-Core Processor
AMD64 Family 23 Model 113 Stepping 0, AuthenticAMD
Microcode signature: 00000000
HTT             *       Multicore
HYPERVISOR      -       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             *       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          *       Supports AMD SKINIT

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            *       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              -       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          *       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           *       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX intruction extensions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          *       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             *       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           *       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           -       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
INVPCID         -       Supports INVPCID instruction
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
TSC-INVARIANT   *       TSC runs at constant rate
xTPR            -       Supports disabling task priority messages

EIST            -       Supports Enhanced Intel Speedstep
ACPI            -       Implements MSR for power management
TM              -       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          -       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             -       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 00000010 (Basic), 80000020 (Extended).

Logical to Physical Processor Map:
**------------------------------  Physical Processor 0 (Hyperthreaded)
--**----------------------------  Physical Processor 1 (Hyperthreaded)
----**--------------------------  Physical Processor 2 (Hyperthreaded)
------**------------------------  Physical Processor 3 (Hyperthreaded)
--------**----------------------  Physical Processor 4 (Hyperthreaded)
----------**--------------------  Physical Processor 5 (Hyperthreaded)
------------**------------------  Physical Processor 6 (Hyperthreaded)
--------------**----------------  Physical Processor 7 (Hyperthreaded)
----------------**--------------  Physical Processor 8 (Hyperthreaded)
------------------**------------  Physical Processor 9 (Hyperthreaded)
--------------------**----------  Physical Processor 10 (Hyperthreaded)
----------------------**--------  Physical Processor 11 (Hyperthreaded)
------------------------**------  Physical Processor 12 (Hyperthreaded)
--------------------------**----  Physical Processor 13 (Hyperthreaded)
----------------------------**--  Physical Processor 14 (Hyperthreaded)
------------------------------**  Physical Processor 15 (Hyperthreaded)

Logical Processor to Socket Map:
********************************  Socket 0

Logical Processor to NUMA Node Map:
********************************  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
**------------------------------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
**------------------------------  Instruction Cache   0, Level 1,   32 KB, Assoc   8, LineSize  64
**------------------------------  Unified Cache       0, Level 2,  512 KB, Assoc   8, LineSize  64
********------------------------  Unified Cache       1, Level 3,   16 MB, Assoc  16, LineSize  64
--**----------------------------  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
--**----------------------------  Instruction Cache   1, Level 1,   32 KB, Assoc   8, LineSize  64
--**----------------------------  Unified Cache       2, Level 2,  512 KB, Assoc   8, LineSize  64
----**--------------------------  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
----**--------------------------  Instruction Cache   2, Level 1,   32 KB, Assoc   8, LineSize  64
----**--------------------------  Unified Cache       3, Level 2,  512 KB, Assoc   8, LineSize  64
------**------------------------  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
------**------------------------  Instruction Cache   3, Level 1,   32 KB, Assoc   8, LineSize  64
------**------------------------  Unified Cache       4, Level 2,  512 KB, Assoc   8, LineSize  64
--------**----------------------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**----------------------  Instruction Cache   4, Level 1,   32 KB, Assoc   8, LineSize  64
--------**----------------------  Unified Cache       5, Level 2,  512 KB, Assoc   8, LineSize  64
--------********----------------  Unified Cache       6, Level 3,   16 MB, Assoc  16, LineSize  64
----------**--------------------  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**--------------------  Instruction Cache   5, Level 1,   32 KB, Assoc   8, LineSize  64
----------**--------------------  Unified Cache       7, Level 2,  512 KB, Assoc   8, LineSize  64
------------**------------------  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**------------------  Instruction Cache   6, Level 1,   32 KB, Assoc   8, LineSize  64
------------**------------------  Unified Cache       8, Level 2,  512 KB, Assoc   8, LineSize  64
--------------**----------------  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**----------------  Instruction Cache   7, Level 1,   32 KB, Assoc   8, LineSize  64
--------------**----------------  Unified Cache       9, Level 2,  512 KB, Assoc   8, LineSize  64
----------------**--------------  Data Cache          8, Level 1,   32 KB, Assoc   8, LineSize  64
----------------**--------------  Instruction Cache   8, Level 1,   32 KB, Assoc   8, LineSize  64
----------------**--------------  Unified Cache      10, Level 2,  512 KB, Assoc   8, LineSize  64
----------------********--------  Unified Cache      11, Level 3,   16 MB, Assoc  16, LineSize  64
------------------**------------  Data Cache          9, Level 1,   32 KB, Assoc   8, LineSize  64
------------------**------------  Instruction Cache   9, Level 1,   32 KB, Assoc   8, LineSize  64
------------------**------------  Unified Cache      12, Level 2,  512 KB, Assoc   8, LineSize  64
--------------------**----------  Data Cache         10, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------**----------  Instruction Cache  10, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------**----------  Unified Cache      13, Level 2,  512 KB, Assoc   8, LineSize  64
----------------------**--------  Data Cache         11, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------**--------  Instruction Cache  11, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------**--------  Unified Cache      14, Level 2,  512 KB, Assoc   8, LineSize  64
------------------------**------  Data Cache         12, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------**------  Instruction Cache  12, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------**------  Unified Cache      15, Level 2,  512 KB, Assoc   8, LineSize  64
------------------------********  Unified Cache      16, Level 3,   16 MB, Assoc  16, LineSize  64
--------------------------**----  Data Cache         13, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------**----  Instruction Cache  13, Level 1,   32 KB, Assoc   8, LineSize  64
--------------------------**----  Unified Cache      17, Level 2,  512 KB, Assoc   8, LineSize  64
----------------------------**--  Data Cache         14, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------**--  Instruction Cache  14, Level 1,   32 KB, Assoc   8, LineSize  64
----------------------------**--  Unified Cache      18, Level 2,  512 KB, Assoc   8, LineSize  64
------------------------------**  Data Cache         15, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------**  Instruction Cache  15, Level 1,   32 KB, Assoc   8, LineSize  64
------------------------------**  Unified Cache      19, Level 2,  512 KB, Assoc   8, LineSize  64

Logical Processor to Group Map:
********************************  Group 0
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